The invention generally relates to integrated circuit chips and media for interconnecting same. More particularly, the invention relates to assemblies known as multichip modules (MCM) wherein unpackaged integrated circuit chips can be mounted on and wired to a substrate containing multiple patterned metal levels for power distribution and signal interconnection.
An MCM generally comprises a substrate on which are formed patterned conductive regions for the interconnection of circuit components, usually integrated circuit chips. The conductive regions are usually made of metal and formed in multiple levels, referred to herein as metal or interconnection levels or layers.
It is known that a substrate of an MCM can be fabricated of a variety of materials such as silicon, ceramic (for example, alumina), glass, or metal (for example, aluminum). It is also known that an interconnection level or layer can be formed on the substrate by depositing, sputtering, evaporating, in combination sputtering and plating, or by some other technique a conductive region on a given layer. The conductive region then can be patterned into signal and power distribution conductors by photolithographic techniques combined with etching or selective plating. Multiple interconnection levels or layers can be formed so long as suitable interposing insulating layers are provided.
Interposing levels of insulating dielectric, i.e., insulating layers disposed between interconnection layers, can be applied by spinning, in the case of polymers, or chemical or physical vapor deposition, in the case of organics such as silicon dioxide. Holes (vias) patterned in these insulating layers by photolithography and wet or dry etching techniques allow interconnection from one level of metal to another.
An MCM substrate provides an interconnection medium for a plurality of chips that is more advantageous than, for example, printed circuit boards to which are mounted individually packaged chips, because it dramatically reduces the distance required for signals to travel between chips, and thus the time delay for inter-chip signal propagation. As integrated circuit technology has continued to advance higher circuit speeds, this interconnection delay has become a major limitation on system performance, and thus has increased the importance of MCMs as interconnection media.
Also, for electronic systems, the use of an MCM and unpackaged chips advantageously results in far greater packing density of chips, and thus reduced system size.
A disadvantage of present MCM systems of packaging and interconnection systems has been the high cost of MCM fabrication. The fabrication process is similar to that for integrated circuits (IC), and manufacturing equipment designed for integrated circuits generally has been used to fabricate MCMs, although an older generation of equipment generally can be used since MCM feature sizes are considerably larger than IC feature sizes. The manufacturing process of MCMs is essentially sequential, and the cost is roughly proportional to the number of photolithographic masks used in fabrication.
In this regard, it is common practice for MCM manufacturers to use at least four metal or interconnection levels, and thus eight or more masks, to provide for both power distribution and signal interconnections. Typically, there is one level each for a power plane, a ground plane, signals in the X direction, and signals in the Y direction. A mask is used for each level to pattern the conductive regions or conductors, and then another mask is used at each level to pattern the holes (vias) in the intervening dielectric to the next interconnection level.
The uppermost layer of an MCM usually is a dielectric which protects the entire structure, and whose pattern of openings to underlying conductive regions allows connections to be made between chips or the MCM package and the substrate itself by means of wire bonds, solder bumps, or other interconnection means.
In some substrate manufacturing technologies, additional masks are required for top level metallization compatible with wire bond or solder interconnect processes. It is also common to include some form of capacitor dielectric for decoupling purposes between the large area power and ground planes, and this dielectric must be patterned with yet another mask. All of these mask levels contribute to fabrication complexity and cost, and each manufacturing step in some incremental manner contributes to the inevitable yield loss due to manufacturing defects.
The combined maximum wiring density in a set of MCM signal planes generally can exceed 2,000 inches of wire per square inch of substrate. Yet, except in areas of the highest wiring congestion, most MCM designs use only a fraction of the available wiring capacity on the signal planes.
It is known that a pair of solid power distribution planes, one plane for power and one plane for ground, form an extremely low inductance power distribution system for relatively noise-free power delivery to semiconductor chips. It is also known that sandwiching a thin layer of dielectric material between these planes creates a distributed decoupling capacitor with very good high frequency characteristics. For example, see U.S. Pat. No. 4,675,717, the disclosure of which is incorporated herein by reference. Further, advances in discrete capacitor technology have resulted in decoupling capacitors with extremely low internal inductance. The use of these capacitors with a pair of power distribution planes also can result in a relatively noise-free power distribution environment. For example, see Tummala, et al. "Ceramics Packaging with Ferroelectric Decoupling Capacitor", IEEE International Symposium on Applications of Ferroelelctrics, 1990, pp. 28-30, the disclosure of which is fully incorporated herein by reference.
It is also known that a solid power distribution plane can be perforated with an array of holes with little change in the electrical characteristics thereof. Such planes are commonly used in MCMs on layers which overlay polymer dielectrics, to allow outgassing of the polymer during curing. The resulting structure is known as a mesh plane.
Further, both power and ground potentials can be distributed on one physical layer by means of a technique referred to as interdigitation. In interdigitation, long, thin conductive regions are provided on one layer for carrying power and ground potentials or signals. The power and ground regions are alternatively arranged so that every other region carries power potentials or signals while the interposing regions carry a ground potential. In this technique, however, if the conductors are long and thin, parasitic inductance and resistance detrimental to noise-power-free distribution are introduced. See H. Schettler, "Passive-Silicon-Carrier Design and Characteristics", 40th Electronic Components and Technology Conference, Las Vegas, May 20-23, 1990, pp. 559-561.